In addition to reading and writing operations, graphics memory devices generally perform screen refresh operations. Because of this additional functionality, graphics memory devices typically must operate at higher operating speeds than traditional memory devices. To meet these speed demands, high-speed synchronous DRAM devices have frequently been used for graphics memory applications. For example, FIG. 1 is a block diagram of a conventional synchronous DRAM device. In this device, a memory cell array 11 is provided along with a write driver 13 and a read driver 17. A data input buffer 15 is also provided in addition to a data output buffer 19. These buffers are generally responsive to a single clock signal CLK.
In particular, during a write operation, data received at a data port DQ is buffered by the data input buffer 15. This data is then transferred to a data input line DI by the data input buffer 15. This transfer operation is performed in-sync with the clock signal CLK. The write driver 13 then drives an input/output line I/O with the data so that the data can be written into the memory cell array 11 using conventional techniques. As illustrated by FIGS. 1-2, after receipt of a read command, read data is transferred from the memory cell array 11 to the read driver 17. The read driver 17 then drives the data output line DO with the read data. The data output buffer 19 buffers the read data and passes the read data to the data port DQ in-sync with each rising edge of the clock signal CLK.
In order to improve the operating speed of such synchronous DRAM devices, Dual Data Rate (DDR) synchronous DRAM devices have been developed. To achieve higher operating frequencies, such devices typically include output buffers that transmit read data to a single output port in-sync with both rising and falling edges of the clock signal. Notwithstanding this higher rate of data transmission, the use of a single output port may limit the ability of DDR DRAM devices to function adequately as graphics memory devices since screen refresh operations may also need to be performed via the single port in addition to normal reading and writing operations. Conventional dual-port memory devices, such as Extended Data Out (EDO) memory devices, typically perform data input and output operations in parallel through two ports. Unfortunately, because such devices typically operate at relatively low frequencies, they also may not be suitable for graphics memory device applications. Thus, notwithstanding the above described memory devices, there continues to be a need for integrated circuit memory devices that can provide improved performance and are more suitable for graphics memory applications.